The invention relates to a method for fabricating a back-illuminated image sensor.
Such a method is, for example, known from US 2006/0186560 A1, which discloses a typical process flow for forming back-illuminated image sensors. This process flow comprises the following steps: First of all, a starting substrate is provided which can be either a silicon on insulator substrate with a silicon top layer with a thickness of about 500 nm or less or a bulk semiconductor substrate. Subsequently, a doping step is carried out to highly dope (N+ or P+) the silicon layer over a thickness of about 50 nm to 500 nm. The surface of the starting substrate is then prepared for a subsequent epitaxial growth step during which an epitaxial silicon layer with a thickness of about 1.5-5 μm is grown. This layer is lightly doped. Over this bi-layer structure (highly doped and lightly doped silicon layer), the electronic devices, such as CMOS imaging components etc, charge couple devices (CCD) components, are then formed using standard microelectronic processing from front end of the line through the back end of the line, i.e. the metallization steps.
Subsequently, a dielectric layer such as a TEOS or a nitride layer is deposited over the electronic devices. The role of this layer is to electrically isolate the back end of the line elements of imaging components and at least partially as a sacrificial layer for the subsequent planarization. The dielectric layer is then planarized, e.g. by chemical mechanical polishing (CMP) technique. The obtained structure is then attached, in particular by bonding, via the surface of the planarized dielectric layer to a handle wafer. The handle wafer can be a bare Si wafer with the native oxide or an oxidized Si wafer. The backside of the original starting substrate, thus the side opposite to where the electronic devices are provided, is then submitted to a Si material removal step, e.g. by grinding and TMAH etching. Following the material removal, the bi-layer structure of the highly doped and lowly doped silicon layer come closer to the backside surface. In case of a silicon on insulator substrate, the removed material can also incorporate the buried oxide (BOX) in the original SOI wafer, which can be removed by HF dip. Depending on the kind of sensor, the BOX can, however, also remain. Eventually, in a subsequent step, further additional layers, such as an anti-reflection lens etc, are fabricated over the bi-layer surface to obtain the final product.
US 2008/0224247 A1 proposes a different approach by first providing sensing elements on the front side of a substrate, to then carry out a thinning step of the backside and to subsequently carry out an implantation of p-type ions via the backside. To activate the implanted p-type dopants, a laser annealing is carried out.
The following problems can occur with the known methods for fabricating a backside illuminated image sensor, in particular with the method of the first prior art document mentioned above. The process steps of doping of the silicon layer, i.e. the necessary cleaning and the subsequent epitaxial growth step can lead to the degradation of physical and electrical properties of the buried semiconductor layers resulting in lower minority carrier lifetimes and increase in the dark current. Furthermore, the diffusion of dopants in the buried semiconductor layers during the processing of the electronic devices (e.g. the CMOS processing) dictates the need for thicker—typically about 1-3 μm thicker than standard layers which are in a range of 1-5 μm—silicon epitaxial layers underneath the photodiodes of the image sensor. In the second case, the electrically active fraction of the dopants is not sufficient.
The present invention now provides an improved method for fabricating a back-illuminated image sensor with improved active dopant profiles.
Accordingly, the improved method comprises the steps of: a) providing a first substrate comprising a semiconductor layer, in particular a silicon layer, b) forming electronic device structures over and/or in the semiconductor layer, c) removing, at least partially, the first substrate, d) amorphization of at least a part of the semiconductor layer and e) doping the semiconductor layer, in particular the amorphized region.
By carrying out the doping step after having fabricated the electronic devices for the image sensor, like CMOS or CCD components or pixel circuits, the invention enables a more precisely defined doping profile in the semiconductor layer, and unwanted diffusion of dopants is reduced as the doping step is moved towards the end of the fabrication process.
As there is no need for an additional silicon layer epitaxial growth to form the photoactive region, this area of the image sensor will be better protected from parasitic contamination and, as a consequence, an improved device performance can be achieved.
In addition, the step of amorphization of at least a part of the semiconductor layer and the doping enables a more efficient activation at a given temperature and thus a desired activation quality and/or efficiency can be obtained at lower temperatures compared to the prior art. This also allows to better protect the already fabricated electronic devices. In this context, amorphization means that the to be doped region is rendered amorphous.
Typically, the dopants, e.g. boron for p-type doping or As for n-type doping, are introduced by an ion implantation technique, however a plasma treatment could also be used.
The amorphization step can be preferably carried out before the doping step. In this case channelling distortions of the dopant ions can be prevented. By doing so, a better process control can be achieved, e.g. a more uniform doping across the wafer.
Nevertheless, according to a variant, the amorphization and the doping step can be carried out at the same time or the amorphization can also be carried out after the doping.
Preferably, the step of amorphization can comprise implanting ions of at least one of silicon, germanium, argon or xenon into the semiconductor layer or a plasma treatment. This represents an effective way of providing an amorphous layer. In case that amorphization and doping are carried out at the same time, a device using two ions beams, one for doping and one for amorphization can be used.
As dopants, one can e.g. use boron for a p-type dopant profile and phosphorus or arsenic for a n-type dopant profile.
Advantageously, the method can further comprise a step f) after step b) and before step c) of forming a levelling layer over the electronic device structures. With this layer, the flexibility of the process can be enhanced, by levelling, e.g. accompanied by a planarization, e.g. by CMP.
Preferably, the method can comprise a step g) after step f) of attaching, in particular by bonding, a second substrate to the levelling layer. Instead of bonding, attaching can also be achieved by an adhesive means. The second substrate provides mechanical support to the structure.
According to an advantageous variant, during step e), the doping can occur via the side opposite to the side where the electronic device structures are provided. Thus a negative impact on the fabricated electronic devices can be prevented.
Advantageously, the method can further comprise a step h) of activating the dopants. Preferably, this step h) can be carried out such that the temperature of the region comprising the electronic device structures is 450° C. or less. By doing so, the properties of already formed electronic components, e.g. junctions, will e.g. be less disturbed by diffusion. Additionally, the low temperature dopant activation process can prevent a degradation of metal interconnect layers due to melting.
According to a preferred embodiment, step h) can be carried out by the conventional thermal anneal (furnace or Rapid thermal processing), which, is preferably carried out at less than 450° C. (temperature in the region of the electronic devices), will lead to the removal of implant damage and the electrical activation of the dopants. During such an anneal a phenomenon called “solid phase epitaxial recrystallization”, i.e. re-growth of the amorphous layer occurs. This step is of particular interest in case of electrical activation of boron as a doping species.
According to a variant laser, in particular, pulsed laser annealing can be advantageously used to activate the dopant in the amorphized layer. The pulsed laser annealing is preferably done in a melting regime. The advantage of the amorphization before laser anneal is as follows: The melting temperature of amorphous Si is significantly lower than that for the crystalline Si: 1420 K vs. 1690 K. For example, a KrF excimer laser (248 nm wavelength, pulse duration of about 20 ns) with the pulse energy density of about 0.5-0.6 J/cm2 can be used to melt amorphous Si layers with a thickness of up to 50-60 nm and result high electrical activation of the dopants. The laser annealing of the amorphized layers allows to reduce the effective processing temperature in the regions of already formed electronic components compared to the prior art without amorphized layers.
According to another variant, a microwave activation can be advantageously used to activate the implanted dopants when the thickness of the layers (after thinning), is for example, more than 100 μm.
According to a preferred variant of the invention, step c) can be carried out such that only the semiconductor layer or a part thereof remains. Thus, light can reach the device from the backside, thus the side opposite to where the electronic device structures are provided, and the desired carrier concentrations can be created in the semiconductor layer.
Preferably, the first substrate can be one of a silicon wafer, a silicon on insulator wafer, a silicon germanium on insulator wafer (SiGeOI), a silicon germanium alloy (SiGe alloy), a germanium on insulator wafer (GeOI), a germanium wafer (Ge) and a gallium arsenide (GaAs) wafer.
In the case that a semiconductor on insulator type substrate is used, step c) can be carried out such that the grinding stops around 10-20 μm above the buried oxide (BOX). The following TMAH etch stops at the BOX. The BOX itself can then be left over or also removed. For the bulk substrates, the grinding stops around 10-20 μm above the bonding interface.
Further preferred, step f) can comprise forming a dielectric layer, in particular a TEOS or nitride layer. Thus levelling and electrical isolation can be achieved. Preferably, the dielectric deposition step can be followed by CMP planarization.
Advantageously, the second substrate can be one of a silicon wafer, a poly-Si substrate, a glass substrate and a quartz substrate. Actually, the main role of the second substrate is to provide the desired stability to the structure. Therefore, any kind of substrate which is readily available is suitable. Nevertheless materials are preferred which ensure close thermal expansion coefficients between the two substrates to prevent breaking of the bonded pair during a subsequent thermal treatment.
According to a preferred embodiment, step e) can comprise forming of a doping pattern, in particular of first zones with a first doping type and second zones, preferably in zones complementary to the first zones, with a second doping type. Patterning may be achieved by using a patterned mask. This feature improves the flexibility of the application.
Preferably, the electronic devices can comprise at least one of CMOS devices, CCD devices, photodiodes, phototransistors, pixel circuits and optoelectronic devices. For these kind of products a well defined dopant concentration profile leads to improved products.